1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to the design and manufacture of floating gate memory devices such as flash electrically erasable programmable read-only memory (EEPROM) devices having improved and more uniform performance characteristics.
2. Description of the Related Art
Computer systems and other modern electronic equipment typically store information in electronic memories. Although the types of memories vary widely, most of such memories, if not all, store information in binary form as a series of logical ones and zeros. In many ways, memories are analogous to a set of switches; if a particular switch is on, it provides a logical one, and conversely, if the switch is off, it provides a logical zero. Information is thus stored by selectively turning the various switches on and off.
A flash electrically erasable programmable read only memory (EEPROM), for example, typically comprises an array of cells that may each be selectively switched on and off. For example, U.S. Pat. No. 4,698,787, to Mukherjee et al., issued Oct. 6, 1987, describes in detail the structure and operation of such a flash EEPROM.
More specifically, referring to FIGS. 1 and 2, a flash EEPROM device typically comprises an N.times.M array 104 of individual memory cells 110 and various control circuits (not shown) for programming, reading, and erasing cells 110. Each cell 110, as shown in FIG. 1, typically includes: a double-diffused n-type source 112 and an n-type drain 114 formed in a p-type substrate 116; a channel 118 disposed in substrate 116 between source 112 and drain 114; a floating gate 122 overlying channel 118 and overlapping the edges of drain 114 and source 112; a layer of dielectric, known as the tunnel dielectric 120, separating floating gate 122 from source 112, drain 114, and channel 118; a control gate 126 overlying floating gate 122; and a second layer of dielectric, known as the interpoly dielectric 124, separating floating gate 122 from control gate 126. Double-diffused source 112 is commonly formed by performing a first relatively light diffusion driven deep into the substrate, followed by a second higher density but shallower doping. When a voltage in excess of a threshold value is applied to the control gate 126 of a cell 110, and when proper biasing conditions are applied to source 112 and drain 114, channel 118 of the cell conducts electrons 136 from source 112 to drain 114 of the cell.
Array 104 (FIG. 2) typically includes a large number of cells 110, e.g. 1,000 or more, arranged in a series of rows and columns. Each row is driven by an associated word line (WL), comprising a conductive polysilicon layer that forms control gate 126 of each cell 110 within the row. Each column is driven by an associated bit line (BL) comprising an overlying layer of metal connected to each drain 114 of the cells 110 within the column. The cells in a column are arranged such that adjacent cells share a common semiconductor region as source or drain regions. Source 112 of each cell 110 within array 104 is coupled to a common source line CS formed by a conductive path diffused in substrate 116. Any individual cell 110 within array 104 can be individually addressed (programmed and read) by operating upon one word line and one bit line.
Referring again to FIG. 1, an individual cell 110 is programmed by charging floating gate 122 through high energy electron injection, often referred to as hot electron injection. By applying the appropriate potentials to source 112, drain 114, and control gate 126, hot electrons 136A are injected from channel 118 through tunnel dielectric 120 to negatively charge floating gate 122. Charging floating gate 122 with a negative potential raises the threshold voltage of cell 110 by a predetermined amount V.sub. from a first nominal value V.sub.T1 to a second nominal value V.sub.T2. As a result,, a programmed cell 110 (V.sub.T &gt;V.sub.T2) conducts substantially less current during a subsequent read operation than an unprogrammed cell 110 (V.sub.T &lt;V.sub.T1) having no charge on floating gate 122.
During a read operation, a predetermined voltage V.sub.G is applied to control gate 126 of selected cell 110. If the selected cell 110 is unprogrammed (V.sub.T &lt;V.sub.T1), the gate voltage V.sub.G exceeds the threshold voltage V.sub.T1 of the cell, and cell 110 conducts a relatively high current (above a predetermined upper threshold level, e.g. 100 microamps). Conduction of such high level current is indicative of a first state, e.g., a zero or logical low. On the other hand, if the selected cell 110 has been programmed (V.sub.T &gt;V.sub.T2), gate voltage V.sub.G is less than the threshold voltage V.sub.T2 of the cell, and the cell is non-conductive, or at least conducts less current (below a predetermined lower threshold level, e.g. 20 microamps). Conduction of such low level current is indicative of a second state, e.g., one or logical high.
In contrast to the programming procedure, flash EEPROMs are typically bulk-erased, so that all of cells 110 in array 104 (i.e. connected to a common source line CS) are simultaneously erased. Appropriate potentials applied to the source 112, drain 114, and control gate 126, cause electron tunneling from floating gate 122 to source 112 or drain 114 via Fowler-Nordheim (F-N) tunneling. For example, electrons 136B stored during programming on floating gate 122 tunnel through tunnel dielectric 120 in a tunnel region 140 where floating gate 122 overlaps source region 112. F-N tunneling occurs simultaneously for all cells 110 within memory array 104, erasing entire array 104 in one "flash" or operation.
Because each cell 110 is connected to common source line CS, all cells 110 in array 104 are erased for the same amount of time. Ideally, each cell 110 in array 104 requires the same amount of time to erase, i.e. to remove electrons 136B from floating gate 122 and achieve a lower selected threshold voltage. Erase times among cells 110 within array 104, however, differ widely. Because of the variation in erase times, each cell 110 must be erased for the amount of time required to erase the slowest cell in array 104. Erasing faster cells 110 for too long, however, results in over-erasure. Over-erasure generates a positive charge on floating gate 122, which excessively lowers the threshold voltage V.sub.T of cell 110, in some instances to the extent of establishing a negative threshold voltage (V.sub.T &lt;0). As a result, the over-erased cell 110 may be continuously activated, even when control gate 126 is grounded (V.sub.G =0 volts), so that cell 110 always conducts during a read operation, regardless of whether over-erased cell 110 is the cell selected for reading. In addition, the increase V.sub. in threshold voltage effected by programming, may not be sufficient to raise the threshold voltage V.sub.T, of the over-erased cell above the predetermined voltage V.sub.G applied to control gate 126 of selected cell 110, so that even when programmed, the over-erased cell conducts upon application of V.sub.G during the read process, giving an erroneous reading.
The current conducted by over-erased cells 110 in a column during a read operation is known as "column leakage current." Column leakage current manifests itself by degrading or destroying the memory's reliability and endurance. As discussed above, the bit value of a selected cell 110 depends on the magnitude of the drain current provided at the associated bit line BL. Drain 114 of each cell 110 in a column, however, is connected to the associated bit line BL. Ideally, the only cell in the column biased for possible conduction is the cell in the selected word line WL; the predetermined voltage V.sub.G is applied to the gates of cells on the selected word line and all other gates are grounded during the reading process. If selected cell 110 is unprogrammed, current in excess of the upper threshold value will be provided on the bit line, indicating e.g., a zero. If the selected cell is programmed with a "1", the drain current of the cell (and, ideally, the bit line), is below the lower threshold value during the read operation. However, the current in the bit line reflects the cumulative current flow from all of the cells in a column. Accordingly, if any of the cells in the column are over-erased and conduct significant current during the read operation, the current flow in the bit line may be in excess of the upper threshold value. Consequently, the read operation generates a logical zero regardless of which cell in the column is selected or whether the selected cell is programmed. In severe cases, a single over-erased cell disables the entire column. In another case, many of the cells may be slightly over-erased which provides a cumulative column leakage current in excess of the upper threshold value. For example, if each cell in a column of 512 cells leaks 0.2 microamps, the total column leakage current is 102.4 microamps, in excess of the upper threshold value of 100 microamps, thereby disabling the entire column. Milder cases may simply degrade the performance of the memory over time, greatly reducing the reliability and endurance of the device, i.e. the number of cycles the device can be successfully programmed and erased.
The problem of over-erasure is recognized but remains unresolved in the prior art. For example, U.S. Pat. No. 5,335,198, to Van Buskirk et al., issued Aug. 2, 1994, discloses an over-erasure correction method, involving sensing an over-erase condition (i.e. when the voltage on floating gate 122 is positive) and individually programming each over-erased cell until the cell is properly erased (i.e., when the positive voltage on the floating gate 122 is eliminated). Disadvantageously, individually reprogramming all of the over-erased bits in an array of cells introduces considerable delay. If many of the cells within an array are over-erased, the time required to correct all of these cells is prohibitive. In addition, the necessary circuitry for sensing an over-erase condition occupies valuable space on the semiconductor substrate.